Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, stacked chip assemblies including the rerouted semiconductor devices, and methods

ABSTRACT

A rerouting element for a semiconductor device that includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations located adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to elements that reroutethe locations of bond pads on semiconductor devices and, morespecifically, to rerouting elements that are configured to be secured tothe active surfaces of fabricated semiconductor devices to reroute thebond pad locations thereof. In addition, the present invention relatesto methods for designing rerouting elements and to rerouting methods.The present invention also relates to multi-chip modules withsemiconductor devices in stacked arrangement and including one or moreof the rerouted semiconductor devices, as well as to methods for formingand packaging such assemblies.

[0003] 2. Background of Related Art

[0004] In order to conserve the amount of surface area, or “realestate”, consumed on a carrier substrate, such as a circuit board, bysemiconductor devices connected thereto, various types of increaseddensity packages have been developed. Among these various types ofpackages is the so-called “multi-chip module” (MCM). Some types ofmulti-chip modules include assemblies of semiconductor devices that arestacked one on top of another. The amount of surface area on a carriersubstrate that may be saved by stacking semiconductor devices is readilyapparent-a stack of semiconductor devices consumes roughly the sameamount of real estate on a carrier substrate as a single, horizontallyoriented semiconductor device or semiconductor device package.

[0005] Due to the disparity in processes that are used to form differenttypes of semiconductor devices (e.g., the number and order of variousprocess steps), the incorporation of different types of functionalityinto a single semiconductor device has proven very difficult to actuallyreduce to practice. Even in cases where semiconductor devices that carryout multiple functions can be fabricated, multi-chip modules thatinclude semiconductor devices with differing functions (e.g., memory,processing capabilities, etc.) are often much more desirable since theseparate semiconductor devices may be fabricated independently and laterassembled with one another much more quickly and cost-effectively (e.g.,lower production costs due to higher volumes and lower failure rates).

[0006] Multi-chip modules may also contain a number of semiconductordevices that perform the same function, effectively combining thefunctionality of all of the semiconductor devices thereof into a singlepackage.

[0007] An example of a conventional, stacked multi-chip module includesa carrier substrate, a first, larger semiconductor device secured to thecarrier substrate, and a second, smaller semiconductor device positionedover and secured to the first semiconductor device. Any suitableadhesive may be used to secure the semiconductor devices to one another.The second semiconductor device does not overlie bond pads of the firstsemiconductor device and, thus, the second semiconductor device does notcover bond wires that electrically connect bond pads of the firstsemiconductor device to corresponding contacts or terminal pads of thecarrier substrate. Such a multi-chip module is disclosed and illustratedin U.S. Pat. No. 6,212,767, issued to Tandy on Apr. 10, 2001(hereinafter “the '767 Patent”). Due to the use of bond wires to formelectrical connections between bond pads and corresponding terminalpads, this type of stacked multi-chip module has been limited to usewith semiconductor devices that include peripherally located bond pads.

[0008] U.S. Pat. No. 5,323,060, issued to Fogal et al. on Jun. 21, 1994(hereinafter “the '060 Patent”) shows one example where dice of the samesize are stacked on top of one another over a circuit board. Bondingwires are connected from the bond pads of each die to correspondingterminal pads on the circuit board. In order to provide clearance forthe bond wires that electrically connect bond pads and correspondingterminal pads, however, adjacent semiconductor devices must be spacedapart from one another a significant distance.

[0009] Stacked multi-chip modules of other configurations have also beendeveloped. For example, it is known that stacked multi-chip modules mayinclude large semiconductor devices positioned over smallersemiconductor devices and that adjacent semiconductor devices may bestaggered relative to one another or have different orientations.

[0010] Different electrical connection technologies, including wirebonding, tape-automated bonding (“TAB”), and controlled-collapse chipconnection (“C-4”), which results in a so-called flip-chip arrangement,are but a few of the ways in which discrete conductive elements may beformed in stacked multi-chip modules. Different electrical connectiontechnologies have also been used in single multi-chip modules, with thebond pads of one semiconductor device being electrically connected tocorresponding contact areas of a carrier substrate of the multi-chipmodule with a different type of discrete conductive element than thatused to form electrical connections between the bond pads of anothersemiconductor device and their corresponding contact areas of thecarrier substrate.

[0011] Many semiconductor devices include bond pads that are arranged atcentral locations on an active surface thereof. Examples includesemiconductor devices that are configured for use with leads-over-chip(LOC) type lead frames, in which the bond pads are arrangedsubstantially linearly along the centers thereof, as well assemiconductor devices with bond pads disposed in an “I” arrangement.While it may be desirable to use such semiconductor devices in stackedmulti-chip modules, the central bond pad placements thereof do notreadily facilitate the use of bond wires or other laterally extendingdiscrete conductive elements to electrically connect the bond pads withtheir corresponding terminal pads of a circuit board that underlies thesemiconductor device stack.

[0012] Accordingly, there are needs for apparatus and methods thatfacilitate the use of semiconductor devices with centrally located bondpads in stacked multi-chip modules. There are also needs for apparatusand methods for reducing the heights of stacked multi-chip modules thatinclude semiconductor devices with peripherally located bond pads.

SUMMARY OF THE INVENTION

[0013] A rerouting element incorporating teachings of the presentinvention includes a substantially planar member, referred to herein asa base substrate, with opposed top and bottom surfaces. The basesubstrate of the rerouting element carries electrically conductive vias,or contacts, that are exposed to the bottom surface thereof and arrangedto mirror a footprint of one or more bond pads on a surface of asemiconductor device, such as an LOC type semiconductor device or asemiconductor device with peripherally arranged bond pads, to which thererouting element is to be secured.

[0014] Each electrically conductive via of the rerouting elementcommunicates with a corresponding conductive trace thereof. Theconductive traces of the rerouting element may be carried internallywithin the substantially planar member, externally on the top or bottomsurface thereof, or some combination thereof. Each conductive traceleads to a corresponding reroute location on the base substrate, atwhich a contact pad is positioned. Upon assembly of the reroutingelement with a semiconductor device complementary thereto, the contactpads of the rerouting element will be located at desired positionsrelative to an active surface of the semiconductor device.

[0015] A rerouted semiconductor device according to the presentinvention includes a semiconductor device with one or more bond pads ona surface thereof and a rerouting element with electrically conductivevias that are positioned to align with corresponding bond pads of thesemiconductor device. The rerouting element is positioned over a bondpad-bearing surface of the semiconductor device with electricallyconductive vias of the rerouting element and corresponding bond pads ofthe semiconductor device in alignment and electrically communicatingwith one another. The rerouting element is secured to the bondpad-bearing surface of the semiconductor device with the conductivetraces and contact pads of the rerouting element being electricallyisolated from underlying structures of the semiconductor device.

[0016] When used in an assembly of stacked semiconductor devices, thererouted semiconductor device may facilitate the positioning of one ormore other semiconductor devices over a central region (i.e., thelocations of substantially centrally positioned bond pads) thereof. Inaddition, a rerouted semiconductor device that incorporates teachings ofthe present invention may facilitate the use of shorter discreteconductive elements to connect rerouted bond pads to correspondingcontact areas of a carrier substrate than would otherwise be required toconnect more centrally located bond pads to their corresponding contactareas.

[0017] Alternatively, the use of a rerouting element that incorporatesteachings of the present invention may facilitate the use ofsemiconductor devices with peripherally located bond pads in assemblieswhich include semiconductor devices that are stacked in staggeredarrangement relative to one another.

[0018] A semiconductor device assembly incorporating teachings of thepresent invention includes a first, rerouted semiconductor device and asecond semiconductor device positioned over the first, reroutedsemiconductor device. When the first and second semiconductor devicesare assembled with one another, the rerouted bond pads of the first,rerouted semiconductor device may be exposed beyond an outer peripheryof the second semiconductor device. Accordingly, the secondsemiconductor device may have smaller dimensions than those of the firstsemiconductor device. Alternatively, the lateral position of the secondsemiconductor device may be staggered relative to the position of thefirst, rerouted semiconductor device, or only partially superimposedover the first semiconductor device. Such a semiconductor deviceassembly may also include a carrier substrate, such as a circuit board,an interposer, another semiconductor device, or leads. Contact areas ofthe carrier substrate correspond to rerouted bond pads of the first,rerouted semiconductor device, as well as to bond pads of the secondsemiconductor device. Discrete conductive elements, such as wire bonds,conductive tape-automated bond (TAB) elements carried by a dielectricsubstrate, or leads, may electrically connect bond pads of the first andsecond semiconductor devices to corresponding contact areas of a carriersubstrate.

[0019] Methods for designing rerouting elements are also within thescope of the present invention, as are methods for forming reroutedsemiconductor devices, methods for assembling semiconductor devices instacked relation, and methods for packaging semiconductor devices.

[0020] Other features and advantages of the present invention willbecome apparent to those of ordinary skill in the art throughconsideration of the ensuing description, the accompanying drawings, andthe appended claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0021] In the drawings, which illustrate exemplary embodiments ofvarious aspects of the present invention:

[0022]FIG. 1 is a top view of an exemplary embodiment of reroutingelement incorporating teachings of the present invention;

[0023]FIG. 2 is a cross-section taken along line 2-2 of FIG. 1;

[0024]FIG. 3 is a top view of an assembly including the reroutingelement of FIGS. 1 and 2 and a semiconductor device with centrallylocated bond pads;

[0025]FIG. 4 is a cross-section taken along line 4-4 of FIG. 3;

[0026]FIG. 4A is a cross-sectional representation depicting anotherexemplary embodiment of rerouting element, which is configured tosubstantially cover a surface of a semiconductor device;

[0027]FIG. 5 is a side view of a stacked two-semiconductor deviceassembly including semiconductor devices and rerouting elements of thetype illustrated in FIG. 4A;

[0028]FIG. 6 is a side view of an exemplary stacked arrangement of anassembly that includes three semiconductor devices and reroutingelements of the type illustrated in FIG. 4A;

[0029]FIG. 7 is a side view of another exemplary stacked arrangement ofan assembly that includes three semiconductor devices and reroutingelements of the type illustrated in FIG. 4A;

[0030]FIG. 8 is a cross-sectional representation of a multi-chip moduleincluding the assembly of FIG. 5, a carrier substrate, an encapsulant,and external connective elements;

[0031]FIG. 9 is a top view of another exemplary embodiment of reroutingelement, which is configured to reroute bond pads of a semiconductordevice with peripherally located bond pads toward a single or twoadjacent edges of the semiconductor device;

[0032]FIG. 10 is a top view of yet another exemplary embodiment ofrerouting element;

[0033]FIG. 11 is a top view of a stacked assembly includingsemiconductor devices and rerouting elements of the type depicted inFIG. 10;

[0034]FIG. 12 depicts the assembly of FIG. 11 secured and electricallyconnected to a carrier substrate; and

[0035]FIG. 13 is a cross-sectional representation of a multi-chip moduleincluding the assembly of FIG. 12, an encapsulant, and externalconnective elements.

DETAILED DESCRIPTION OF THE INVENTION

[0036]FIGS. 1 and 2 depict an exemplary embodiment of a reroutingelement 40, which is configured to be disposed on an active surface 32of a semiconductor device 30 (FIGS. 3 and 4) and to reroute bond pad 34locations of semiconductor device 30. Rerouting element 40 includes abase substrate 41 with a top side 42 and a bottom side 43, electricallyconductive vias 44 exposed at bottom side 43 and extending toward topside 42, at least partially through base substrate 41, conductive traces45 carried by base substrate 41 and extending from a correspondingelectrically conductive via 44 toward an outer periphery 46 of basesubstrate 41 to contact pads 47 located adjacent to outer periphery 46of base substrate 41 and exposed at top side 42 thereof. While contactpads 47 are depicted as being located adjacent to a single peripheraledge 46 a of base substrate 41, rerouting elements that include contactpads positioned proximate to two adjacent edges of the base substratesthereof are also within the scope of the present invention.

[0037] As base substrate 41 of rerouting element 40 is configured to bedisposed on active surface 32 of semiconductor device 30, base substrate41 need only have sufficient dimensions to cover active surface 32 or aportion thereof.

[0038] Base substrate 41 maybe formed from a dielectric material, suchas a nonconductive polymer (e.g., polyimide). In addition, basesubstrate 41 may comprise a flexible, relatively thin, substantiallyplanar member, enabling base substrate 41 to minimize package heightand, as desired, to conform somewhat to surfaces that are located atdifferent elevations (e.g., the different elevations of a multi-chipmodule). It is currently preferred that base substrate 41 comprise aflex tape, such as that used to fabricate a TAB element. Alternatively,base substrate 41 may comprise substantially planar member formed fromany other dielectric material (e.g., glass, ceramic, etc.) or at leastpartially dielectric-coated semiconductor material or even adielectric-coated metal if heat transfer is to be facilitated.

[0039] As an example and not to limit the scope of the presentinvention, electrically conductive vias 44 may comprise conductivebumps, such as bumps of solder, gold, or another suitable metal or metalalloy. Alternatively, conductive vias 44 may comprise columns, pillars,or other structures that are formed from a suitable, electricallyconductive material, such as a conductive or conductor-filled epoxy oran anisotropically conductive (z-axis) elastomer.

[0040] Conductive traces 45 may, by way of example only, be formed froma low electrical resistance, electrically conductive material, such asaluminum or copper.

[0041] Each conductive trace 45 of rerouting element 40 may extendeither internally through or externally across base substrate 41.Alternatively, each conductive trace 45 may include one or moreinternally and externally carried portions. While it is preferred thatany external portions of conductive traces 45 be carried on top side 42of base substrate 41, conductive traces 45 or portions thereof may alsobe exposed to back side 43.

[0042] While conductive traces 45 may be nonlinear, some or all ofconductive traces 45 may alternatively provide the shortest possiblepath length between a corresponding electrically conductive via 44 andcontact pad 47. Accordingly, substantially straight conductive traces 45are within the scope of the present invention. As another option,conductive traces 45 may be of substantially the same length to matchimpedence and signal speed.

[0043] Adjacent conductive traces 45 are preferably electricallyisolated from one another, either by being spaced apart from one anotheron base substrate 41 or by the material of base substrate 41 locatedtherebetween. In addition, conductive traces 45 may be positioned,oriented, and spaced on base substrate 41 relative to one another insuch a manner as to reduce or eliminate any electrical interferencetherebetween. Conductive traces 45 of rerouting element 40 may beparallel or nonparallel to one another.

[0044] Contact pads 47 are carried upon either top side 42 of basesubstrate 41 at or adjacent to a peripheral edge 46 thereof or onperipheral edge 46. Such positioning of contact pads 47 facilitatesaccess thereto by equipment that will secure discrete conductiveelements 56 (FIG. 8) to contact pads 47 (e.g., a wire bonding capillary,ultrasonic bonding equipment, thermocompression bonding equipment,etc.).

[0045] Portions of base substrate 41 that underlie conductive traces 45may electrically isolate conductive traces 45 from an active surface 32of an underlying semiconductor device 30 (FIGS. 3 and 4). Alternatively,or in addition, at least portions of back side 43 of base substrate 41may be coated with an adhesive material 48, such as a thermoset resin ora pressure-sensitive adhesive. Such a coating of adhesive material 48may facilitate securing of rerouting element 40 to an active surface ofa semiconductor device 30 (FIGS. 3 and 4). Adhesive material 48 may alsoelectrically insulate conductive traces 45 and contact pads 47 fromunderlying features of a semiconductor device 30 upon which reroutingelement 40 is positioned, or provide an additional insulative layer orstandoff distance that decreases or eliminates any electricalinterference that may occur between semiconductor device 30 andconductive traces 45 or contact pads 47.

[0046] A rerouted semiconductor device 20 that includes a reroutingelement 40 and a semiconductor device 30 is illustrated in FIGS. 3 and4. Semiconductor device 30 includes centrally located bond pads 34 onactive surface 32 thereof. As depicted, bond pads 34 are arranged in asubstantially linear manner, in a so-called leads-over-chip (LOC)configuration.

[0047] Rerouting element 40 is positioned on active surface 32, overbond pads 34 and adjacent to at least one peripheral edge 36 ofsemiconductor device 30. Rerouting element 40 may be secured to activesurface 32 by way of adhesive material 48.

[0048] Electrically conductive vias 44 of rerouting element 40, whichare positioned adjacent a peripheral edge 46 of base substrate 41, alignwith corresponding bond pads 34 so that electrical connections may beestablished therewith. By way of example only, electrical connectionsand, thus, electrical communication may be established by way ofphysical contact between electrically conductive vias 44 and theircorresponding bond pads 34. Alternatively, discrete connective elementsformed from a conductive material, such as solder, conductive orconductor-filled epoxy, or anisotropically conductive (z-axis)elastomer, may physically and electrically connect each electricallyconductive via 44 of rerouting element 40 to its corresponding bond pad34 of semiconductor device 30.

[0049] Upon positioning rerouting element 40 on active surface 32 andalignment of electrically conductive vias 44 with their correspondingbond pads 34, contact pads 47 of rerouting element 40 are locatedadjacent to peripheral edge 36 of semiconductor device 30. Thus, eachelectrically conductive via 44, along with its corresponding conductivetrace 45 and contact pad 47, reroutes a corresponding bond pad 34 onactive surface 32 of semiconductor device 30 from a central location tothe more peripheral location at which contact pad 47 is positioned.

[0050]FIG. 4A depicts a variation of rerouted semiconductor device 20′,which includes a semiconductor device 30 and a variation of reroutingelement 40′ on active surface 32 thereof. Rerouting element 40′ includesa base substrate 41′ that is sized to be superimposed over a greaterarea of active surface 32 than base substrate 41 of rerouting element40. As shown, electrically conductive vias 44′ of rerouting element 40′are positioned centrally with respect to base substrate 41′, rather thanadjacent to a peripheral edge 46′ thereof. As will be seen from theensuing description, a rerouting element 40′ of this configuration maysupport another semiconductor device 30 superimposed thereover withgreater stability than rerouting element 40, particularly if basesubstrates 41 and 41′ are fairly thick.

[0051] Referring now to FIG. 5, a semiconductor device assembly 10 isshown that includes two rerouted semiconductor devices 20 a′, 20 b′ instacked, or superimposed, relation. As shown, the upper semiconductordevice 20 b′ is staggered relative to the next lower reroutedsemiconductor device 20 a′, with contact pads 47 of semiconductor device20 a′ being exposed laterally beyond an outer periphery 36 ofsemiconductor device 30 b and, thus, beyond an outer periphery ofrerouted semiconductor device 20 b′.

[0052] A back side 33 of the semiconductor device 30 b of the upperrerouted semiconductor device 20 b′ is spaced apart from active surface32 of the semiconductor device 30 a of the lower rerouted semiconductordevice 20 b′, at least in part, by way of rerouting element 40′. Backside 33 of semiconductor device 30 b is secured to a top side 42′ ofbase substrate 41′ and, thus, of rerouting element 40′ by way ofadhesive material 49 therebetween.

[0053] Electrically conductive vias 44 and any externally carriedportions of conductive traces 45 that extend between the adjacentsemiconductor devices 30 a and 30 b may be electrically isolated fromback side 33 of the upper semiconductor device 30 b by way of dielectricadhesive material 49 that secures back side 33 to top side 42′.Alternatively, the material of base substrate 41′ may electricallyisolate electrically conductive vias 44 and conductive traces 45 fromback side 33 when electrically conductive vias 44 do not extend fullythrough the thickness of base substrate 41′ and the portions ofconductive traces 45 that are located between semiconductor devices 30 aand 30 b are carried internally by base substrate 41′. Of course,electrically conductive vias 44 and conductive traces 45 may also beelectrically isolated from back side 33 of the next higher semiconductordevice 30 b by any combination of dielectric adhesive material 49 andbase substrate 41′ material.

[0054]FIGS. 6 and 7 illustrate stacked semiconductor device assemblies10′ and 10″, respectively, which include more than two reroutedsemiconductor devices 20′. In FIG. 6, contact pads 47 of each reroutedsemiconductor device 20 a′, 20 b′, 20 c′ are positioned adjacent thesame peripheral edge 16 a′ of assembly 10′. Rerouted semiconductordevices 20 a′, 20 b′, 20 c′ are progressively staggered to facilitatethe securing of discrete conductive elements 56 (FIG. 8) to each contactpad 47.

[0055] Assembly 10′ FIG. 7 includes rerouted semiconductor devices 20a′, 20 b′, 20 c′ that are arranged with contact pads 47 of the upper andlower rerouted semiconductor devices 20 a′ and 20 c′ being positionedadjacent to the same peripheral edge 16 a″ of assembly 10″ and contactpads 47 of the central rerouted semiconductor device 20 b′ beingpositioned adjacent to an opposite peripheral edge 16 b″ assembly 10″.To facilitate electrical connection to contact pads 47 of each reroutedsemiconductor device 20 a′, 20 b′, 20 c′, rerouted semiconductor devices20 a′, 20 b′, 20 c′ are arranged in repeating staggered relation. Statedanother way, while rerouted semiconductor device 20 b′ is only partiallysuperimposed over rerouted semiconductor device 20 a′, reroutedsemiconductor device 20 c′ is completely superimposed over reroutedsemiconductor device 20 a′. The distance between contact pads 47 of thelowermost rerouted semiconductor device 20 a and back side 33 ofsemiconductor device 30 c of the uppermost rerouted semiconductor device20 c′ may be sufficient to provide access by discrete conductive elementpositioning or forming equipment (e.g., a wire bonding capillary,thermocompression bonding equipment, ultrasonic bonding equipment, etc.)to contact pads 47 of rerouted semiconductor device 20 a′. In any event,the spacing between top side 42′ of rerouting element 40′ of reroutedsemiconductor device 20 a′ and back side 33 of semiconductor device 30 cof rerouted semiconductor device 20 c′ is sufficient for discreteconductive elements 56 (FIG. 8) to extend therebetween.

[0056] As shown in FIG. 8, a semiconductor device package 50 includingassembly 10 is depicted. In package 50, rerouted semiconductor device 20a′ of assembly 10 is secured to a carrier substrate 52, such as thedepicted circuit board, an interposer, another semiconductor device, orleads of a lead frame. Contact pads 47 of rerouted semiconductor devices20 a′ and 20 b′ are electrically connected to, or communicate with,corresponding contact areas 54 of carrier substrate 52 by way ofdiscrete conductive elements 56, such as the depicted bond wires,conductive traces carried upon a flexible dielectric substrate to form aTAB element, thermocompression or ultrasonically bonded leads, or thelike, that extend therebetween. Package 50 may also include a protectiveencapsulant 58 that may surround rerouted semiconductor devices 20 a′and 20 b′, discrete conductive elements 56, and portions of carriersubstrate 52 located adjacent to rerouted semiconductor device 20 a′. Byway of example only, protective encapsulant 58 may comprise a moldedstructure (e.g., a pot molded or transfer molded structure) or aso-called “glob top” type structure of viscous dielectric material.

[0057]FIG. 9 depicts another example of a routing element 40″ for usewith a semiconductor device that includes bond pads positioned adjacentto more than one peripheral edge thereof to reroute the locations of thebond pads of such a semiconductor device to locations adjacent oneperipheral edge or two adjacent peripheral edges of the semiconductordevice.

[0058] Rerouting element 40″ is configured similarly to reroutingelements 40 and 40′, but includes electrically conductive vias 44″ thatare positioned adjacent an outer periphery 49″ of base substrate 41″ atlocations on top side 42″ thereof that correspond to the locations ofbond pads on the active surface of the semiconductor device over whichrerouting element 40″ is to be positioned. Of course, conductive traces45″ of rerouting element 40″ extend from corresponding electricallyconductive vias 44″ to contact pads 47″ positioned adjacent either oneperipheral edge 49 b″ or two adjacent peripheral edges 49 a″, 49 b″ ofbase substrate 41″.

[0059] A rerouted semiconductor device including rerouting element 40″may be assembled with one or more other rerouted semiconductor devices20″, 20′, or other semiconductor devices that include bond pads that areeach positioned adjacent to either a single peripheral edge thereof ortwo adjacent peripheral edges thereof in a similar manner to theassemblies depicted in FIGS. 5-7.

[0060] As rerouting element 40″ reroutes bond pads from locations thatare adjacent to three or four peripheral edges thereof to locations thatare adjacent to one or two peripheral edges thereof, stacked assembliesof decreased height may be achieved when rerouting element 40″ is used.This can be seen in FIGS. 11-13, which, although described in terms ofrerouting element 40′″ of FIG. 10, depict an exemplary staggeredstacking arrangement that can be used when a rerouting element 40″ withcontact pads 47″ adjacent to one or two peripheral edges 49 a″, 49 b″thereof is used with a semiconductor device that includes bond padsarranged around three or four peripheral edges thereof.

[0061] Turning now to FIG. 10, another exemplary embodiment of reroutingelement 40′″ is depicted. Rerouting element 40′″ includes a basesubstrate 41′″ , electrically conductive vias 44′″, conductive traces45′″ and contact pads 47′″ that are substantially the same as thecorresponding elements of rerouting elements 40 and 40′ (FIGS. 1-8).Again, electrically conductive vias 44′″ are positioned correspondinglyto bond pads 34 positioned centrally on an active surface 32 of asemiconductor device 30 over which rerouting element 40′″ is to bepositioned. However, contact pads 47′″ of rerouting element 40′″ arepositioned adjacent to more than one peripheral edge 46′″ of basesubstrate 41′″.

[0062] Rerouted semiconductor devices 20′″ formed by assemblingrerouting elements 40′″ with a complementarily configured semiconductordevices 30 may be used in any appropriate, known type semiconductordevice assembly or multi-chip module, such as in the stacked assembly10′″ depicted in FIG. 11.

[0063]FIG. 12 depicts stacked assembly 10′″ secured to a carriersubstrate 52′″ in an exemplary fashion. Although carrier substrate 52′″is shown as comprising an interposer, it may alternatively be in theform of a circuit board, a lead frame, another semiconductor device, orany other suitable substrate known in the art. Contact areas 54′″ ofcarrier substrate 52′″ may communicate with corresponding contact pads47′″ of each rerouted semiconductor device 20′″ or other semiconductordevice of assembly 10′″ by way of discrete conductive elements 56 (e.g.,bond wires, TAB elements, thermocompression or ultrasonically bondedleads, etc.) placed or formed therebetween. Of course, it is preferredthat discrete conductive elements 56 be electrically isolated from oneanother, as well as from any other structures (e.g., semiconductordevices 30) over which they extend.

[0064] As shown in FIG. 13, stacked assembly 10′″ and carrier substrate52′″ may be incorporated into a package 50′″ . Package 50′″ may alsoinclude a protective encapsulant 58′″ that covers at least portions ofeach rerouted semiconductor device 20′″ or other semiconductor device ofassembly 10′″, discrete conductive elements 56, and regions of carriersubstrate 52′″ that are located proximate an outer periphery of assembly10′″. Protective encapsulant 58′″ may comprise a glob top typeencapsulant, as depicted, or any other known type of semiconductordevice encapsulant, such as a pot molded encapsulant or a transfermolded encapsulant.

[0065] Referring again to FIGS. 1-4, a method for designing a reroutingelement 40 that incorporates teachings of the present invention includesidentifying a semiconductor device 30 with bond pads 34 to be rerouted,as well as determining the locations of rerouting element 40 to whichbond pads 34 are to be rerouted. Accordingly, the design method includesconfiguring electrically conductive vias 44 of rerouting element 40 tobe positioned correspondingly to bond pads 34 of the identifiedsemiconductor device 30. Conductive traces 45 of rerouting element 40are configured to extend from the locations of correspondingelectrically conductive vias 44, with which conductive traces 45communicate, to a desired, reroute location on a base substrate 41 ofrerouting element 40. In addition, contact pads 47 are configured at thedesired, reroute locations of base substrate 41.

[0066] Returning reference to FIGS. 5 and 8, an assembly methodincorporating teachings of the present invention includes providing acarrier substrate 52 and securing a first rerouted semiconductor device20 a′ to carrier substrate 52. Rerouted semiconductor device 20 a′ maybe secured to carrier substrate 52 by way of an adhesive material 53(e.g., a pressure sensitive adhesive, a thermoset resin, a thermoplasticelastomer, etc.) disposed between superimposed regions of reroutedsemiconductor device 20 a′ and carrier substrate 52.

[0067] A second semiconductor device, such as the depicted reroutedsemiconductor device 20 b′ or any other semiconductor device includinginput/output pads that are arranged in a fashion that may be used instacked multi-chip modules, may be positioned over reroutedsemiconductor device 20 a′. Rerouted semiconductor device 20 b′ isdepicted as being only partially superimposed over reroutedsemiconductor device 20 a′, with contact pads 47 of the lower reroutedsemiconductor device 20 a′ being exposed beyond an outer periphery 26′of the upper rerouted semiconductor device 20 b′. Alternatively, asdepicted in FIGS. 13 and 14, the upper semiconductor device may besubstantially superimposed over the lower semiconductor device.

[0068] Contact pads 47 of each semiconductor device 20 a′, 20 b′ may beelectrically connected to and, thus, electrically communicate withcorresponding contact areas 54 of carrier substrate 52 by forming orpositioning discrete conductive elements 56 between correspondingcontact pads 47 and contact areas 54. Such positioning may be effectedat any time that appropriate discrete conductive element-forming or-positioning equipment may access contact areas 47, including, withoutlimitation, prior to the placement of a second semiconductor device(e.g., rerouted semiconductor device 20 b′) over first reroutedsemiconductor device 20 a′ and after the semiconductor devices (e.g.,rerouted semiconductor devices 20 a′ and 20 b′) have been assembled withone another in stacked relation.

[0069] Although the foregoing description contains many specifics, theseshould not be construed as limiting the scope of the present invention,but merely as providing illustrations of some exemplary embodiments.Similarly, other embodiments of the invention may be devised which donot depart from the spirit or scope of the present invention. Featuresfrom different embodiments may be employed in combination. The scope ofthe invention is, therefore, indicated and limited only by the appendedclaims and their legal equivalents, rather than by the foregoingdescription. All additions, deletions, and modifications to theinvention, as disclosed herein, which fall within the meaning and scopeof the claims are to be embraced thereby.

What is claimed is:
 1. A semiconductor device assembly, comprising: afirst semiconductor device including a surface with at least one bondpad located substantially centrally thereon; a rerouting elementpositioned over said first semiconductor device, said rerouting elementcomprising: a substantially planar member including a top surface and abottom surface; at least one contact exposed at said bottom surface andpositioned correspondingly to a position of said at least one bond pad;at least one conductive trace corresponding to and extending laterallyaway from said at least one contact toward a periphery of saidsubstantially planar structure; at least one rerouted bond padcorresponding to said at least one conductive trace, said at least onererouted bond pad being located proximate a periphery of said firstsemiconductor device; and a second semiconductor device positioned overa portion of said rerouting element, said at least one rerouted bond padbeing exposed beyond a periphery of said rerouting element.
 2. Thesemiconductor device assembly of claim 1, wherein said firstsemiconductor device comprises a plurality of bond pads, at least someof which are located substantially centrally on said surface.
 3. Thesemiconductor device assembly of claim 2, wherein said rerouting elementcomprises: a plurality of contacts positioned correspondingly to saidplurality of bond pads; a plurality of conductive traces incommunication with corresponding contacts of said plurality of contacts;and a plurality of rerouted bond pads in communication withcorresponding conductive traces of said plurality of conductive traces.4. The semiconductor device assembly of claim 3, wherein each reroutedbond pad of said plurality of rerouted bond pads is at least partiallyexposed beyond a periphery of said second semiconductor device.
 5. Thesemiconductor device assembly of claim 3, wherein each rerouted bond padof said plurality of rerouted bond pads is located laterally adjacent aperiphery of said first semiconductor device.
 6. The semiconductordevice assembly of claim 5, wherein each rerouted bond pad of saidplurality of rerouted bond pads is located adjacent a single edge ofsaid first semiconductor device.
 7. The semiconductor device assembly ofclaim 1, wherein said first semiconductor device comprises a leads-overchip type semiconductor device having at least one central row of bondpads.
 8. The semiconductor device assembly of claim 1, wherein saidfirst semiconductor device comprises a I-bond pad arrangement.
 9. Thesemiconductor device assembly of claim 1, further comprising a carriersubstrate.
 10. The semiconductor device assembly of claim 9, whereinsaid first semiconductor device is secured to said carrier substrate.11. The semiconductor device assembly of claim 9, where in said carriersubstrate comprises at least one of a circuit board, an interposer,another semiconductor device, and leads.
 12. The semiconductor deviceassembly of claim 9, wherein said at least one rerouted bond pad is incommunication with a corresponding contact area of said carriersubstrate.
 13. The semiconductor device assembly of claim 12, furthercomprising: a discrete conductive element positioned between said atleast one rerouted bond pad and said corresponding contact area.
 14. Thesemiconductor device assembly of claim 13, wherein said at least onediscrete conductive element comprises at least one of a bond wire, atape-automated bond element trace, and a lead.
 15. The semiconductordevice assembly of claim 1, wherein said second semiconductor deviceincludes at least one bond pad located substantially centrally on asurface thereof.
 16. The semiconductor device assembly of claim 15,further comprising: another rerouting element on a bond pad-bearingsurface of said second semiconductor device.
 17. The semiconductordevice assembly of claim 1, wherein said second semiconductor device isoriented in staggered relation to said first semiconductor device. 18.The semiconductor device assembly of claim 1, wherein said secondsemiconductor device is smaller than said first semiconductor device.19. The semiconductor device assembly of claim 1, further comprising: atleast one additional semiconductor device positioned over said secondsemiconductor device.
 20. The semiconductor device assembly of claim 13,further comprising: an encapsulant protecting at least portions of saidfirst semiconductor device, said second semiconductor device, said atleast one discrete conductive element, and portions of said carriersubstrate located laterally adjacent outer peripheries of said first andsecond semiconductor devices.
 21. The semiconductor device assembly ofclaim 20, wherein said encapsulant comprises a glob top typeencapsulant.
 22. The semiconductor device assembly of claim 20, whereinsaid encapsulant comprises a transfer molding compound.
 23. Thesemiconductor device assembly of claim 20, further comprising: at leastone external connective element in communication with said at least onebond pad of said first semiconductor device.
 24. A method for designinga rerouting element for use with a semiconductor device including atleast one bond pad positioned substantially centrally on a surfacethereof, comprising: configuring at least one contact location on afirst surface of a substantially planar member, said at least onecontact location mirroring a position of the at least one bond pad onthe surface of the semiconductor device; configuring at least oneconductive trace location extending from said at least one contactlocation toward a periphery of said substantially planar member; andconfiguring at least one rerouted bond pad location proximate saidperiphery, said at least one rerouted bond pad position being configuredto be exposed beyond a periphery of another semiconductor device uponpositioning the other semiconductor device over the surface of thesemiconductor device.
 25. The method of claim 24, wherein saidconfiguring at least one contact location comprises configuring aplurality of contact locations, each contact location of said pluralityof contact locations mirroring a location of a corresponding bond pad onthe surface of the semiconductor device.
 26. The method of claim 25,wherein said configuring at least one conductive trace locationcomprises configuring a plurality of conductive trace locations, eachconductive trace location of said plurality of conductive tracelocations extending from a corresponding contact location toward aperiphery of said substantially planar member.
 27. The method of claim26, wherein each conductive trace location of said plurality ofconductive trace locations extends toward a single edge of saidsubstantially planar member.
 28. The method of claim 26, wherein saidconfiguring at least one rerouted bond pad location comprisesconfiguring a plurality of rerouted bond pad locations, each reroutedbond pad location of said plurality of rerouted bond pad locations beingcontinuous with an end of a corresponding conductive trace location andlocated proximate a periphery of said substantially planar member. 29.The method of claim 28, wherein each rerouted bond pad location of saidplurality of rerouted bond pad locations is configured to be exposedbeyond a periphery of the other semiconductor device upon positioning ofthe other semiconductor device over the surface of the semiconductordevice.
 30. The method of claim 24, wherein said configuring said atleast one rerouted bond pad location comprises configuring said at leastone rerouted bond pad location to facilitate connection of a discreteconductive element thereto with the other semiconductor devicepositioned over the surface of the semiconductor device.
 31. A methodfor assembling semiconductor devices in a stacked arrangement,comprising: providing a semiconductor device with at least one bond padpositioned substantially centrally on a surface thereof; and positioninga rerouting element over said surface of said semiconductor device witha contact of said rerouting element communicating with said at least onebond pad, a circuit trace of said rerouting element extending laterallytoward a periphery of said semiconductor device and establishingcommunication between said at least one bond pad and a rerouted bond padlocated proximate a periphery of said semiconductor device at a locationwhere said at least one rerouted bond pad will remain exposed uponpositioning another semiconductor device over said surface.
 32. Themethod of claim 31, wherein said providing said semiconductor devicecomprises providing a semiconductor device with a plurality of bondpads, at least some of which are positioned at substantially centrallocations on said surface.
 33. The method of claim 32, wherein saidproviding said rerouting element comprises providing a rerouting elementcomprising: a plurality of contacts, each contact of said plurality ofcontacts being positioned correspondingly to a position of acorresponding bond pad of said semiconductor device; a plurality ofconductive traces, each conductive trace of said plurality of conductivetraces extending laterally from a corresponding contact of saidplurality of contacts toward a periphery of said semiconductor device;and a plurality of rerouted bond pads, each rerouted bond pad of saidplurality of rerouted bond pads being positioned at an end of acorresponding conductive trace, proximate said periphery of saidsemiconductor device.
 34. The method of claim 33, wherein said providingsaid rerouting element comprises providing a rerouting element with eachrerouted bond pad of said plurality of rerouted bond pads beingpositioned proximate a single peripheral edge of said semiconductordevice.
 35. The method of claim 33, wherein said providing saidrerouting element comprises providing a rerouting element with eachrerouted bond pad of said plurality of rerouted bond pads beingpositioned to be exposed beyond a periphery of another semiconductordevice upon being positioned over said surface of said semiconductordevice.
 36. The method of claim 31, further comprising: positioning saidanother semiconductor device over said rerouting element, said at leastone rerouted bond pad of said rerouting element being exposed beyond aperiphery of said another semiconductor device.
 37. The method of claim36, further comprising: securing said semiconductor device to a carriersubstrate.
 38. The method of claim 37, wherein said securing comprisessecuring said semiconductor device to at least one of a circuit board,an interposer, an additional semiconductor device, and the leads. 39.The method of claim 37, further comprising: positioning at least onediscrete conductive element between said at least one rerouted bond padand a corresponding contact area of said carrier substrate.
 40. Themethod of claim 39, wherein said positioning comprises at least one ofwire bonding, tape-automated bonding, and thermocompression bonding. 41.The method of claim 37, further comprising: encapsulating at leastportions of said at least one semiconductor device, said anothersemiconductor device, and regions of said carrier substrate adjacent tosaid semiconductor device.
 42. The method of claim 41, wherein saidencapsulating comprises glob top encapsulating.
 43. The method of claim41, wherein said encapsulating comprises one of transfer molding and potmolding.
 44. A rerouting element for use with a semiconductor device,comprising: a base substrate; a plurality of conductive vias positionedadjacent at least two peripheral edges of said base substrate, eachconductive via of said plurality of conductive vias being located so asto align with a corresponding, peripherally located bond pad of thesemiconductor device upon assembly of said rerouting element with thesemiconductor device; a plurality of conductive traces; and a pluralityof contact pads, each conductive trace of said plurality of conductivetraces extending from a corresponding conductive via toward at least oneother peripheral edge of said base substrate to a corresponding contactpad of said plurality of contact pads.
 45. The rerouting element ofclaim 44, wherein said plurality of conductive vias are positionedadjacent three peripheral edges of said base substrate.
 46. Thererouting element of claim 45, wherein each contact pad of saidplurality of contact pads is positioned adjacent to another, singleperipheral edge of said base substrate.
 47. The rerouting element ofclaim 44, wherein said plurality of conductive vias are positionedadjacent to two adjacent peripheral edges of said base substrate. 48.The rerouting element of claim 47, wherein each contact pad of saidplurality of contact pads is positioned adjacent to at least one of twoother adjacent peripheral edges of said base substrate.
 49. A reroutingelement for use with a semiconductor device, comprising: a basesubstrate; a plurality of conductive vias, at least some of which arepositioned centrally on said base substrate, each conductive via of saidplurality of conductive vias being located so as to align with acorresponding bond pad of the semiconductor device upon assembly of saidrerouting element with the semiconductor device; a plurality ofconductive traces; and a plurality of contact pads, each conductivetrace of said plurality of conductive traces extending from acorresponding conductive via toward at least one peripheral edge of saidbase substrate to a corresponding contact pad of said plurality ofcontact pads.
 50. The rerouting element of claim 49, wherein saidplurality of conductive vias are arranged in at least one line extendingcentrally across said base substrate.
 51. The rerouting element of claim49, wherein each contact pad of said plurality of contact pads islocated adjacent a single peripheral edge of said base substrate. 52.The rerouting element of claim 51, wherein each contact pad of saidplurality of contact pads is located adjacent to at least one of twoadjacent peripheral edges of said base substrate.